The present disclosure relates to an imaging device, a method of manufacturing the same, and an electronic apparatus, and more particularly, to an imaging device capable of providing superior pixel characteristics, a method of manufacturing the same, and an electronic apparatus.
In the related art, in an amplification type solid-state imaging device as represented by a CMOS (Complementary Metal Oxide Semiconductor) image sensor, charges are transferred from a photoelectric conversion device (photodiode) which is present at a deep position from a front surface of a semiconductor substrate to the vicinity of the front surface.
For example, as one of a method of transferring charges, a technique using a vertical transistor is disclosed in Japanese Unexamined Patent Application Publication No. 2008-258316. The vertical transistor is formed by forming a trench (vertical groove) by dry etching from a front surface side of a semiconductor, by forming a gate insulation film, and then by inserting a gate electrode.
Further, a technique in which a vertical transistor is used and charges which are photoelectrically converted can be efficiently lifted from a photodiode which is present at a deep position to be transferred to a floating diffusion region is disclosed in Japanese Unexamined Patent Application Publication No. 2010-114274.
Further, it is possible to achieve a small area of pixel size by using the vertical transistor, compared with a structure in which a conductive well which is the same as a photodiode disclosed in Japanese Unexamined Patent Application Publication No. 2006-278446 is used as a transfer path. Particularly, since it is necessary to lift charges from a photodiode which is present at a deep position for transfer in a vertical spectral imaging device, it is effective to apply a vertical transistor structure so as to realize a vertical spectral imaging device of small pixels.
The vertical transistor structure in the related art will be described with reference to FIGS. 1A and 1B. Figs. 1A and 1B are cross-sectional views illustrating a configuration example of a solid-state imaging device in which a vertical transistor is formed. An upper side in Figs. 1A and 1B is a front surface side of the solid-state imaging device, and a lower side in Figs. 1A and 1B is a rear surface side of the solid-state imaging device.
As shown in FIG. 1A, in a solid-state imaging device 11, a PD (Photodiode) 13 is disposed at a deep position of a semiconductor substrate 12, and an FD (Floating diffusion) 14 is disposed on a front surface side of the semiconductor substrate 12. Further, a gate insulation film 15 is formed on the front surface of the semiconductor substrate 12 and a trench formed from the front surface side of the semiconductor substrate 12, and a gate electrode 16 is inserted into the trench. Further, an anti-reflection film 17 and an oxide film 18 are stacked on the rear surface side of the semiconductor substrate 12.
In such a solid-state imaging device 11, as voltage is applied to the gate electrode 16, the vertical transistor 19 has a structure in which charges accumulated on the PD 13 are transferred to the FD 14 by photoelectric conversion.
However, in a manufacturing process of the vertical transistor 19, it is difficult to control the depth of the trench when the trench is formed on the semiconductor substrate 12, and thus, the depth of the trench varies for each pixel. Thus, as shown in FIG. 1B, the interval between the gate electrode 16 which forms the vertical transistor 19 and the rear surface of the semiconductor substrate 12 varies, and this variation badly affects pixel characteristics.
That is, the variation in the interval between the vertical transistor 19 and the rear surface of the semiconductor substrate 12 is caused by the variation in the depth control in a dry etching process of forming the vertical transistor 19, or may be caused by variation in the film thickness of the semiconductor substrate 12. Further, the variation in the film thickness of the semiconductor substrate 12 is emphasized in a semiconductor substrate thinning process of a rear surface irradiation type semiconductor manufacturing process. Further, the variation in the interval between the vertical transistor 19 and the rear surface of the semiconductor substrate 12 may be referred to as a variation in the interval between the PD 13 which is present at a deep position from the front surface side of the semiconductor substrate 12 and a bottom section of the vertical transistor 19 or a variation in the cover amount. Since the interval between the PD 13 and the bottom section of the vertical transistor 19 considerably affects the transfer efficiency of the charges which are photoelectrically converted, it is necessary to suppress the variation as small as possible.
Thus, in a rear surface irradiation type imaging device in which light irradiates the rear surface of the semiconductor substrate 12, it is effective to employ a penetration-type vertical transistor structure in which the vertical transistor 19 is formed by allowing the gate electrode 16 to penetrate the semiconductor substrate 12 up to the rear surface thereof.
Next, the penetration-type vertical transistor structure will be described with reference to FIGS. 2A to 2C. FIGS. 2A to 2C are cross-sectional views illustrating a configuration example of a solid-state imaging device of the penetration-type vertical transistor structure. An upper side in FIGS. 2A to 2C is a front surface side of the solid-state imaging device, and a lower side in FIGS. 2A to 2C is a rear surface side of the solid-state imaging device.
As shown in FIG. 2A, in a solid-state imaging device 11′ of the penetration-type vertical transistor structure, a penetration-type vertical transistor 19′ is configured by inserting a gate electrode 16′ into the trench formed to penetrate the semiconductor substrate 12 up to the rear surface thereof. In a penetration-type vertical transistor 19′ with such a configuration, the depth of the gate electrode 16′ becomes the same for each pixel, and the above-described variation is removed.
However, in the solid-state imaging device 11′, a gate insulation film 15′ is not formed on a tip end surface side of the gate electrode 16′, and thus, the tip end surface of the gate electrode 16′ is in contact with an anti-reflection film 17. Thus, as shown in FIG. 2B, there is a problem that electric current (gate leakage current) flows between the semiconductor substrate 12 and the gate electrode 16′ through the anti-reflection film 17 in a tip end section of the penetration-type vertical transistor 19′, in the solid-state imaging device 11′ of the penetration-type vertical transistor structure.
Particularly, as shown in FIG. 2C, in a manufacturing process, the anti-reflection film 17 formed on the rear surface side of the semiconductor substrate 12 is formed so that the gate insulation film 15′ of the tip end section of the penetration-type vertical transistor 19′ retreats and the anti-reflection film 17 is interposed between the semiconductor substrate 12 and the gate electrode 16′. In this case, the gate leakage current easily flows between the semiconductor substrate 12 and the gate electrode 16′. Further, the gate leakage current easily flows in a similar way to a case where the oxide film 18 is formed between the semiconductor substrate 12 and the gate electrode 16′.
The generation of the gate leakage current is caused by deterioration of the film quality of the anti-reflection film 17 and the oxide film 18 which are formed on the rear surface side. That is, since it is difficult to form the materials formed on the rear surface side at a high temperature due to the limit of heat-resisting temperature of an additive on a metal wiring layer or a wafer bonding surface, the film quality deteriorates, and electric current easily flows compared with the insulation film formed in the front surface process. Thus, if the anti-reflection film 17 and the oxide film 18 are formed in a region between the semiconductor substrate 12 and the gate electrode 16′ to which an electric field is applied or in the vicinity thereof, the gate leakage current is generated between the semiconductor substrate 12 and the gate electrode 16′.